Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have to dismantle a GNU source code of size nearly 20MB. In order to do so I need information of compile time settings, library linked with it etc. Normally the configure and makefile contains these information. But it is difficult to extract it manually. How to make use of autotools to...
I will rephrase my question. My prime concern is HOW TO INTERPRET THE CONFIG/MAKEFILE? which are provided with the open source codes. In other words I need to get information upon the files, directories, libraries it generates/uses/links to build it.
Normally the GNU Code are provided with configure and make files to build the application. For refactoring/enhancement I need to transfer it to an IDE. So the build information which is inside those config and make files are needed to build them in an IDE. Is there any application which can...
Bit Rate
While specifying a codec, their bit rate are specified. What that numerical value quantify?
For example if I say a codec works at 12.2 Kbps what does that number mean?
Wimax is a wireless broadband standard. The fixed and mobile tells about the range of access.
Fixed Wimax: Broadband access range is fixed. An analogy is cordless handset. The wireless router is an example.
Mobile Wimax: Broadband access can be made where ever you go. An analogy is cellular...
RTP/RTSP HELP NEEDED
Hello all,
I wish to know the implementation of streaming protocols (RTP/RTSP). I'm from DSP background. I have very little knowledge in networking fundas. I find it difficult to interpret the standards. Also the codes available in internet are not to the point. I tried...
Adder
I wish to design a 32 bit adder. So result at the max can be 33 bits. But my output is 32 bits. Hence I should conditionally shift by one bit if the carry is set when 32nd bit is added. How can this be implemented in Verilog for RTL?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
