Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have looked at this also. It appears that most of the command sets are the same. I think that they are going to have to be considering several people (sandisk, toshiba, etc) have generated ASIC for ATA to flash support. No vendor wants to get locked into a single source chip.
I did find...
ntsc pal secam decoder ip
casual3_2002,
I remember seeing this post.
https://www.opencores.com/forums/video/2003/10/00000
There was quite a few other nasty replies that I remember seeing from people that were hoping to use this for products.
There seemed to be a bit of a pissing match...
I think that you are going to have to put in a request to the factory for this one. I check out all of my CDs (and I have good number of them from SIG/PHILIPS) over many years. This AN did not show up anywhere but the high level design guide under IC01. It appears to be a performance report...
Re: Best C compiler for AVR
What ramesh is refering to is the version of im@gecraft. The pro version has a post compile optimizer, the standard version does not. If he compiled under the standard version, that might be the size discrepancy. At one point in time, I looked at the...
Re: Rocket I/O
I am currently doing a design right now.
The main question is what is the speed of the serdes connection that you are going to use? This is somewhat dependant upon the part you pick.
robotman
I have been working on something similar. I want to get to the data too, but I have the intention of multiplexing multiple image sensors over one link.
What I would do is to develop a SDRAM (DDR preferably) controller using a small FPGA. To help increase then bandwidth to the SDRAM, use burst...
biphase mark
Just a note of warning.....
I have done some VCXO/DLL designs in the past. The DLL's are very sensitive to jitter and frequency change. I have even had instances where the DLL just won't recover with a reset, it requires powering down the device. This is not very good...
dpll recovers the clock
A couple of things come to mind.
Most circuits that I have seen that perform this function use a much higher frequency to oversample the input and make decisions. This allows for better jitter control. A digital filter can be used to estimate the adjustments to the...
vcxo fpga
What is your control mechanism for the external vcxo? Integrator? DAC? other?
What is the clock rate of the data? Is is the same as the vcxo?
Can you attach a partial schematic?
robotman
Re: NTSC/PAL Encoder's register spec or the theory of the en
There is a NTSC encoder on the opencores page... There might be some documentation there.
robotman
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
