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Indeed. You're right. The BITCLK is an output in LM4550 primary codec mode, and I should be able to generate the 24.576 MHz clock from it. However I still need the 22.5792 MHz clock, and yet again it seems that the PLL is too limited for this. Ah well, I can always add two external crystal...
I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low...
Ok, sorry for putting words in your mouth ;-)
However, I'm still confused. The balanced sine you showed show only one phase, with a neutral changing in voltage. With a symmetric 3-phase system, the (virtual) neutral doesn't change in voltage (with a Y-coupled load)
Ah.. but therein lies my confusion, you've captured in nicely. The 564VDC would be correct if the line voltage was driven by two phases 180 degree apart, in essence like having a full bridge driven by 564VDC resulting in peak to peak voltage of 2 x 564 V = 400 VAC rms. But the phases are 120...
Which I'd assume is the same as 3 half-bridges ? ;) (i.e. a half bridge consist of 2 semiconductors)
This is for a UPS style system, so frequency is fixed at 50/60Hz. I also see that with the 3 half bridge system I'd need, just as FvM pointed out, 2 * 230 * sqrt(2) ~= 650 VDC in the DC bus...
Not sure what you mean by "balanced" but I'm planning to create the three phases with 3 half-bridges, I suppose this would be considered "non-balanced" ?
Hi, I aim to build a 3-phase inverter (PWM) with output 3x230VAC (Y, 3x400VAC Delta), but I'm confused as to how calculate which DC link voltage is needed for the required outputs ?
TIA
/R
But that can only be fully utilized, I assume, with the rest of the design using the FP core being pipelined ? Anyways, thanks, I think I'll stick to fixed point atm :)
Just out of curiosity for an FPGA-noob, what kind of performance is to be expected for such a beast ? I'm planning on doing a synth engine, and having access to floating-point math would make things a lot easier...
Well, I suppose the data path width would be quite wide, since there are a number of parameters and state variables that need to be propagated down to their correct pipeline stage. The design is still very conceptual (that is, only in my head), so alternative approaches/ideas are welcomed :)
Hi all, I'm setting up a synth engine and I thought I'd pipeline it so I can get high voice count throughput, however, I'm estimating (very roughly) that I'll get somewhere between 30 to 50 pipeline stages. Is this "off the chart" when it comes to pipelining, or is it within reasonable bounds ...
Did you, or did TrickyDicky solve the problem with his suggestion above ? That information would help others experiencing the same problem, which is after all, the whole point of forums/mailing lists. So please state exactly how the problem was solved. Thanks.
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