Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by robertzhan

  1. R

    delay(several us) for PWM signal

    Dear Vishwa and echo47 Sorry to express my appreciation so late since I'm on business last few days. Thank you for your positive suggestions, especially Vishwa's insistent help and support to make my problem solved more quickly than expectation. All the best. :) Best wishes...
  2. R

    delay(several us) for PWM signal

    Dear Vishwa, Thank you for your kind help. yes, I want the replica of the PWM signal at the output after some delay (several microsecond), it's could also deemed as the delayed version of the pwm signal. Thanks. Regards Robert Zhan
  3. R

    delay(several us) for PWM signal

    Dear Vishwa Thank you for your kind help. However, it still doesn't meet my request. The timing edge is not very precise and pwm signal after delay has been affected. The attachment gives the figure to show my aim. Could you tell me how to modify the routine to ensure the delay time and...
  4. R

    delay(several us) for PWM signal

    Dear all, I'd like to make a routine to have a delay for PWM signal, about several microsecond, just like the hold on function. But it emerges the following error: Error: VHDL error at soft_switching.vhd(70): can't infer register for signal "p01:counter[0]" because signal does not hold...
  5. R

    which synthesis tool are you using?

    At the moment, I use Quartus only.
  6. R

    Two rising edge in one process

    Thank you for all ur kind suggestions. I'll think about it more clearly and then to finish it. Best regards Robert Zhan
  7. R

    Two rising edge in one process

    altera_io_begin what is Just as title, I have to detect two rising edge and write the routine as follows. When it was compiled, there is error: Error: VHDL error at soft_switching.vhd(69): can't infer register for signal "counter[0]" because signal does not hold its value outside clock edge I...

Part and Inventory Search

Back
Top