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The images are related to the scenario in which I use the arduino i2c peripheral. According to i2c specifications a minimum time between the fall edge of the SCL and the data change in SDA is 300ns (at least this was what I understood when I read the standard). The only scenario in which these...
Unfortunately I can not do it. I am using the 180nm TSMC library and they don't give the layout of the digital cells, just blockages and general cell sizes.
I already did this, It was the first thing I tried was to do a gate-level timing simulation with the sdf info. Everything works fine in...
Hi,
I did as you suggested and added the 100R/100pF low pass filter but it had no effect. I still have the same type of errors, like the one above where the SDA line is clearly being pushed low by the slave when the master is still transmitting (simultaneous High-to-Low transition on SCL and...
Ok, so you were speaking of oversampling because you are suggesting that the ASIC should have a "system clock". In the company they have a different position regarding it, they say the i2c has to be able to work as a standalone IP, with no extra clock. But I completely understand what you are...
Yes, all the flip-flops are being reset. The system has a global reset pin that forces everything to a known state.
The first thing I test in the simulations is the reset condition and the system's behavior when coming out of reset.
I understand your questions. I did not tell the hole story before I came to the forum asking for help, and therefore, you don't know if I am just another guy searching for an easy answer....
1. I used a simulator to test the design that was sent for fabrication. The ASIC passed all simulation...
Ok, I understand what you are saying. I did not know that the short circuit would look like that on the scope. That means that the slave interface in trying to pull down the line at the wrong time. The slave should only try to pull the line at the 9th clock edge, never before that. I did the...
I know that forcing high is not a good idea, but the circuit has only one master and one slave, and I am only testing write to slave operations.
It was just to try to understand what was happening.
Also, I reduced the pull-up resistors to 1.8K and, in bit bang, it works fine with this...
Hi everyone,
I have a very basic I2C slave ASIC with a bank of registers that I am currently testing. The ASIC was produced just to test the I2C IP (to make sure the design flow was correct and that the IP was ready to be used in more complex projects). According to the simulations and tests...
Ok, its been a long time since I last post something related with this thread, but after a training that I attend and the research and some experiments I got what I needed. I will try to share with you what I learn, it may be useful for other people in this forum.
So, regarding partitioning:
-...
I know of the innovus views and I am used to switch views to see if everything is ok and has it should. I am also used to mask some metal layers to better analyse route results and the design overall.
I am only trying this because I have a part in my design that is really time critical...
Thank you for your time.
I can not figure out what I am doing wrong here. I follow the guide they have on the user guide manual (although some steps are poorly described and probably I am doing some mistake in one of these steps).
I will have a training in September regarding Cadence tools...
I did as you said. I treat the top partition as a regular partition.
I did the place and route flow that I have in the top partition and as expected the cell from the other partition were not considered by innovus.
Then I start another innovus session and execute the following command...
I found out why innovus was issuing an error when i tried to define my partition. It seams that you need to put the partition inside the core are before trying to specify the partition.
Ok I repeated the process using only the command line and my scripts but the final result was the same.
Here...
ok this is gonna be a long post.
I decide to do the process all over again this morning to make sure I was understanding everything.
I open innovus and load my design files along with constraints, lefs, etc.
Then I issue the flooPlan command to set the area I need for the ASIC.
I then proceed...
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