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Re: PIC32 vs ARM
Most of the posters on that forum thread don't have much of a clue about ARM.
ARM processors range from parts costing less than US$1 to 2GHz clock speed devices capable of powering netbooks. There's a lot more ARM processors in the world than there are 8 bit PICs. My...
You can't give the first part of the ERROR response when some other slave is still active.
When HREADYIN is low, it means some other slave is in the data phase (and is extending the data phase). The master is not looking at your HRESP and HREADYout. The two cycle response starts from when the...
diffrence amba versions
I have never seen an AHB slave which does not have both HREADY input and HREADY output.
Quoting from:
**broken link removed**
A key point of slave design that is not made clear by the AHB specification is that slaves will have both HREADYin and HREADYout signals...
BUSY is certainly used by some AHB designs, although many masters do not require it. If you are designing a general purpose slave that can be used in any system, you should make it support BUSY (if it is burst capable). Otherwise, check with the designer of the master to see whether it uses...
ahb lite version 6
It might be helpful if you give a little more detail about the system and what you are trying to achieve.
Have you thought about using a multi-layer AHB-lite system? In that case, you have a point-to-point connection between all masters and all slaves and no need for a...
axi vs ahb
In AHB, there can be only one transaction per master (either a read or a write) at any time.
In which direction does your bridge operate? If you connect a single AHB master to an AHB-> AXI bridge (acting as a slave) and the AXI bridge is a master to an AXI slave, then there is not...
It's more usual to consider the other way around. The program is using a logical/virtual address and the memory management unit in the processor converts that to a physical address to be used by the memory system. The exact way in which that is done depends upon the system, but usually there...
mmnet1001
uCLinux can be run on pretty much every Cortex-M3 port, although the actual level of support obviously varies.
I reviewed a cortex-m3 few boards on our website at:
**broken link removed**
NXP's LPC175x and LPC176x family seem like a good suggestion. They typically have 12bit ADC...
The AHB specification allows systems to be built with databus widths up to 1024 bits, although in practice 32 or 64 bits are the only commonly seen widths. The HSIZE bus allows masters to specify the size of the transfer they want to do - you can still do 8 or 16 bit reads or writes on a wider...
Is your question that you are designing a microprocessor and want to know how to optimize its design? Or are you trying to optimize code for a particular microprocessor?
In the first case - if your processor has an instruction pipeline where you prefetch instructions cycles ahead of executing...
Re: SoC arbiter ?
The AHB specification defines how the grant/request arbitration protocol works, but it's up to you to decide how the arbiter actually decides which master to grant at any particular time.
The common methods used are round-robin arbitration (give each master the bus for a...
Depends upon the purpose of your original question. Were you asking about on-chip buses used to connect processors and memories? If so, there are even simpler on-chip buses than Wishbone & AMBA. And of course things like USB, CAN, PCI, VESA are all widely used buses in computers, but not...
what do you mean by burst bus transaction
It is up to the master how it responds to an Error during a burst. It is allowed to terminate the burst, or to continue the burst. What it does with the error is also up to the master - it can try the access again, or it may be that it reports a problem...
negative setup
Negative set-up time just means that it is permissible for the signal to arrive after the clock edge and there is usually a corresponding increase in hold time.
It can sometimes be seen in situations where there the clock path has a much longer delay than the signal path...
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