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Recent content by riti1

  1. R

    verilog code of 8 dct architecture

    i write the code for 8 dct...but i am getting certain warnings which i cant able to reolve.guide me for the same. module dct_8(clk,x0,x1,x2,x3,x4,x5,x6,x7,y0,y1,y2,y3,y4,y5,y6,y7 ); input clk; input [3:0] x0,x1,x2,x3,x4,x5,x6,x7; output [11:0] y0,y1,y2,y3,y4,y5,y6,y7; wire[10:0]...

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