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Recent content by risccpu

  1. R

    About EMI solution at chip layout stage and board/system

    Hi, Could you please tell me how to reduce noise and/or EMI in the chip layout stage? And how to reduce noise from SOC device to board/system? What are the related EDA tools? Thanks a lot. Best Regards, risccpu
  2. R

    About EMI solution at chip layout stage and board/system

    Hi, Could you please tell me how to reduce noise and/or EMI in the chip layout stage? And how to reduce noise from SOC device to board/system? What are the related EDA tools? Thanks a lot. Best Regards, risccpu
  3. R

    Is there any EDA tool for EMI for Mentor or Cadence

    Neither Mentor nor Cadence has the tool.
  4. R

    Are there any EDA tool for EMI verification software at chip

    Neither Mentor nor Cadence has the tool.
  5. R

    Basic questions about synthesis process

    synthesis question the two major output (files) from the synthesis process: netlist and sdc.
  6. R

    doubt on a delay insertion

    The above paper is very helpful.
  7. R

    help!A question in DC synthesis

    You need to confirm with the datasheet of IO PAD usage and set the according constraints in sdc.
  8. R

    What is the importance of PERL language for VLSI design engineer?

    perl It is very useful to work as a tool to control vlsi flow.
  9. R

    GDSII Viewer and/or print facility ?

    SOC GDS
  10. R

    How important is the selection of scan_in / scan_out pairs?

    scan chain help Hi, When I do dft, I just assign test_scan_in port and test_scan_out port based upon the scan ports given by frontend. Could you tell me what impact by the selections of scan_in and scan_out pairs or the orders of scan_in and scan_out pairs? Or need I do other what work such...
  11. R

    What's the range of capacitance value for a voltage buffer?

    cap. values It depends on the parameters of other components.It maybe 1pf to 10pf.
  12. R

    Help:not annotated nets in Prime Time

    From P&r tools out.
  13. R

    Looking for delta sigma modulator design

    sigma delta circuits An excellent Phd thesis may be a good reference for you. You can search some by google.
  14. R

    Help:not annotated nets in Prime Time

    Could anyone tell me why the list number of not annotated is smaller than the total not annotated number? I use "report_annotated_parasitics -max_nets 100 -list_not_annotated". For example, the report is as following: 1. net1 2. net2 3. net3 4. net4 5. net5...
  15. R

    how can i get the spice parameters of BJT.

    The lateral BJT parameters which are compatible with CMOS process usually base upon a lateral BJT cell, and they were provided by foundaries. For learning, the BJT parameters do not have significent effect on a bandgap reference. You can have a simple model to try it.
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