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module full_sub(a,a1,c,d,b,e);
input a,a1,c;
output reg d,b,e;
always@(a1 or a or c)
begin
e={a,b,c};
case(e)
000:
begin
d=0;
b=0;
end
001:
begin
d=1;
b=1;
end
010:
begin
d=1;
b=1;
end...
hiii everyone,
i m new member of dis forum.....i want to join vrious groups in dis forum.....bt there is join option there....plz guie me hw one can join them.....thanx in advance
module counterdff(clk,d0,d1,d2,q
);
input clk,d0,d1,d2;
output q;
reg q0,q1;
reg q;
always@(posedge clk)
begin
if(clk==1)
q0<=d0;
if(q0<=1)
q1<=d1;
if(q1<=1)
q<=d2;
end
endmodule
i done it by same maanner bt my code is nt synthesizing...plz tell me error
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