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Recent content by rids1

  1. R

    verlog code of sqaure function

    yes we hv to do harware implementation of i x*x...
  2. R

    verlog code of sqaure function

    i want to write verilog code of square function which is synthesizable........guide me plz
  3. R

    verlog code of sqaure function

    i want to write verilog code of x^2...plz guide how i can write a code,,,,which is synthesizable
  4. R

    verilog code of sin wave generation

    i need verilog code of sine wave generator........i tried with cordic algorithm but i cant able to proceed
  5. R

    verilog code of sin wave generation

    i need verilog code of sine wave generator....i tried with cordic algorithm but i cant able to proceed....plzzz help
  6. R

    verilog code of logarithmic function

    I want to write verilog code ,of mathematical function like log(x),x^y,antilog(x),sin or cosine function....how i can write?
  7. R

    full subtractor using case statement...plzz tell me error

    plz tell me hw i can correct it........
  8. R

    Verilog HDL - Book Recommendations

    @Aritra link given by u is nt wrking,,,,plzz upload verilog material somewhere...plzzzzzzzzz
  9. R

    full subtractor using case statement...plzz tell me error

    module full_sub(a,a1,c,d,b,e); input a,a1,c; output reg d,b,e; always@(a1 or a or c) begin e={a,b,c}; case(e) 000: begin d=0; b=0; end 001: begin d=1; b=1; end 010: begin d=1; b=1; end...
  10. R

    xenon equipment

    hello, plz tell me from where one can buy xenon source of intensity 1.5 AM
  11. R

    in order to measure efficiency of solar cell

    hello evryone, i want to measure efficiency of solar cell...plzz tell me source n equipment to measure it in college lab
  12. R

    [MOVED] facing problem in joining group in this forum

    hiii everyone, i m new member of dis forum.....i want to join vrious groups in dis forum.....bt there is join option there....plz guie me hw one can join them.....thanx in advance
  13. R

    [SOLVED] 4 bit ripple counter using four D flip flops

    module counterdff(clk,d0,d1,d2,q ); input clk,d0,d1,d2; output q; reg q0,q1; reg q; always@(posedge clk) begin if(clk==1) q0<=d0; if(q0<=1) q1<=d1; if(q1<=1) q<=d2; end endmodule i done it by same maanner bt my code is nt synthesizing...plz tell me error

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