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Thanks TrickyDicky, I'll try to change my way of doing this, maybe swap to VHDL 2008 will be a better choice for me to use all features of the language. :)
I'm trying to monitor a number of inputs reacting to an output using a procedure, this procedure has as parameters 4 inputs :
- signal INPUTS_OUTPUT which is an array of my inputs and output (Std_logic)
- EXPECTED_VALUE which represent respectively the expected value of my inputs during...
Hello world !
After all, i want to mention that it's my first post in this forum and i'm glad to be a part of EDABOARD network.
In testbench, I have an issue with a procedure that I want to monitor its input parameter which is a signal, this signal may contains a number of my internal inputs...
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