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I am designing LA and CML for optical receiver
but I met problems with LA and CML
Cuz form what i research, LA circuit is almost the same with CML
Can someone tell me what's the difference for LA circuit and CML circuit ?
how does a LA circuit look like and a CML circuit should look like ?
Any...
For L, i make it minimal 0.18um
---------- Post added at 15:53 ---------- Previous post was at 14:50 ----------
Ya bro, doing transimpedance amplifier
---------- Post added at 15:55 ---------- Previous post was at 15:53 ----------
Bro, what if i have the same L with 0.18 while i set...
Is there any reference that i can refer to regarding sizing and noise ?
Then is W/L increase, bandwidth will decrease is it correct ?
How its affect transimepdance gain ?
anyone know how my transistor sizing W/L affect my noise performance ?
From what i simulated out
My result is when i using W=45, L=0.18, my noise is 3.14pA
while W=44, L=0.18, my noise is higher, which is 3.15pA
From what i research, it should be lower rite ?
if we decrease transistor...
Can anyone tell me how W/L affect transimpedance gain ?
From my simulation result, If i increase W/L, transimpeance gain will decrease
Is it correct ?
is there any reference i can find ?
does anyone know the basic schematic for a 1.25Gbps limiting amplifier ?
can post some website where i can find out the circuit diagram ?
i have searched all the internet, but they only have commercialized built-complete circuit and is very complex.
Helps are greatly appreciated
thanks
ya, but my problem is i don't know which value is optimized for my design.Since W value for transaistors MN! and MN2 will effect the gain, and R2 and Rf will also affect my gain.I don't know which to adjust so i can max my transimpedance gain
Anyone out there, Can tell me how do i know that i have already achieved maximum transimpedance gain ?
All i know, i need to fix my L(transistor)=0.18um, and my input current as 30uA.
Circuit
Bandwidth and gain
Currently, i am able to achieve 61dB for this design for 1.25 Gbps.But i don't...
From what i know,
to bias transistor, Vds >Vgs-Vth
Vds>V(overdrive)
but from my simulation,
my Vds is lesser than my Voverdrive (Vgs-Vth)
but why it still displaying saturation mode for MN2 ?
is there any logical explanation ?:-?
Yours response are greatly...
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