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Recent content by RickyRuf

  1. R

    Pin location is too close to PLL clock input pin (Altera MAX10)

    Because the software quartus don't permit me to programm the Pins in this way.
  2. R

    Pin location is too close to PLL clock input pin (Altera MAX10)

    Hello everybody, i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26. Is it possible to disregard this problem? Right now the pin 27 is a clock enable pin used for a crystal that gives the clock for...
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