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Recent content by richloo

  1. richloo

    [HELP] Elab error with Cadence ams(spectre) using VHDL netlist

    Check the datatype for vhdl, some coding style is not compatible with verilog. (eg: array)
  2. richloo

    [HELP] Elab error with Cadence ams(spectre) using VHDL netlist

    ncelab(64): 09.20-s016 1) by using "OSS-based netlister with irun" ERROR: Missing .cdb or .oa file in library c090_phy_lib cell c090_bias view bhv. The OSS netlister requires a .cdb or .oa file in lib/cell/view directory. If one does not exist, you can create one either by importing the...
  3. richloo

    [Help] Problem with onboard regulator

    Hey guys, I got a scenario during power down where my design still have VCCIO (3.3V) stay above my inverter's VIL level. This has translated into my chip is still power on. I have no idea on board design. Does this scenario hold true? How would the industry spec their power supply rail in term...
  4. richloo

    [Help] Ultrasim command usage

    .usim_vr Hi guys, Can anyone tell me how to use .usim_vr to speed up voltage regulator time? Thanks in advance.
  5. richloo

    [Ultrasim]How to load dc operating point

    ultrasim load dc Hey guyz, can u tell me how to load the dcOp.dc into the simulation after my first run on "save DC operating point". I found that the dcOp.dc is a binary file which I cannot use "readic" to load them. Any idea? Thanks in advance.
  6. richloo

    BSIM model design flow

    Can anyone tell me about the design flow on how the bsim model is created? Thanks in advance.
  7. richloo

    ESD device put between the pads

    As long as when the ESD event happened, you can make sure the shortest path to discharge is going through the diode clamp, then it should be fine.
  8. richloo

    What is the diference between I/O cell and Core design?

    I/O vs Core Design Electrically, I/O cell design is usually driven by the external customer specification. However, core design sometimes will have loosen design target which is more likely to take care for overall system. Usually I/O cell design is more customize than core design because the...
  9. richloo

    Ques on coupling effect and optimization for buffer design

    Hi guyz, We have seen coupling effect takes place everywhere in a fast switching single ended buffer circuit. Any material about how to counter the coupling effect? I am currently designing a buffer. How do we actually optimize for the coupling effect between bias generator and the pad seen by...
  10. richloo

    differnce b/w bumps,pads,and IOCELLS

    IOCELL is the IO buffer, pad is for wirebond to the package, bump is used as a connection to the bottom layer for PBGA package.
  11. richloo

    Active RC Filter design questions about OPAMP

    Active RC Filter design The desired filter corner frequency must fall within the unity gain bandwidth of your opamp. So that u can meet the cutoff frequency when u design the 0dB(unity gain) LPF in close-loop. Open-loop gain of the opamp should be as high as possible (~60dB).
  12. richloo

    Parameter analysis of Analog artist of cadence

    ocnprint parametric analysis u can use ocean script with ocnPrint() command to save all point into text file.
  13. richloo

    body source voltage of pmos

    Hi Karthikeya, u r correct too. What i m trying to say is that as long as the bulk and source of the PMOS is connected together, vbs is always zero.
  14. richloo

    How to know that ALL MOS are in saturaion region in Cadence?

    cadence region of operation Maybe u can try to use Annotate voltage on the schematic in conjunction with Circuit conditions to increase your confidence level. If you would like to go into ocean or skill programming, write some script to sweep through all the devices' bias voltage.
  15. richloo

    body source voltage of pmos

    Not necessary at Vdd, it might be at <Vdd. As long as the bulk and the source are connected together.

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