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Recent content by RGR

  1. R

    Clock Transition vs Clock Skew?

    Hello Every one, can any one explain about Which is more important Clock Transition or Clock Skew? Thank you RGR
  2. R

    Regarding Clock Latency and Skew?

    Hai everyone In my project , at cts stage , after clock routing Trail 1: clock skew : 100ps clock latency :600ps Trail 2: clock skew : 200ps clock latency : 400ps Which trail is better and why? please help me.I am using ICC and encounter tool Thank you RGR
  3. R

    What Is Standard cell height in 65nm,130nm and 180nm tecnologies?

    Hello everyone can you please let me know What Is Standard cell height in 65nm,130nm and 180nm tecnologies? Thanks in Advance RGR
  4. R

    How to Calculate the library setup time?

    Hi Every one The library setup and hold times are generally in the library (.db or .lib) and how these are calculated? Here is the Example Report. data arrival time 0.57 clock mck (rise edge) 2.50 2.50 clock network delay (ideal) 0.00 2.50 library setup time -123.44 -120.94 data required...
  5. R

    how to find core area ?

    Hi to every one I am having aspect ratio and Core Utilization. now i want to find out the core area with aspect ratio and utilization is it possible? if possible how to find? Thanks RGR
  6. R

    What HFNS (High fanout net synthesis) in Physical Design?

    hello every one can any one clarify HFNS? Thanks in advance RGR
  7. R

    Why normal buffers don't have equal rise and fall times compared to clock buffers?

    hi can any one clarity about this? Thanks in advance RGR..
  8. R

    what will happen if we dont use filler cells?

    hai coolrak if The filler cells are not used in our design simply DRC violations occurs in your design and yield is also decreases ... Thanqs Regards RGR - - - Updated - - - hai leeenghan may i know the what are the DRC violations we are getting placing nwells of two standard cells...
  9. R

    What is the difference between .v,.db,.ddc format of netlist?

    hello every one can any one explain the difference between .v,.db,.ddc formats of a netlist Thanqs in Advance...... RGR
  10. R

    Implement 8:1 mux using only 4:1 mux?

    hai OhaAmo i didn't get you can you please explain briefly Thanqs in Advance RGR
  11. R

    Implement 8:1 mux using only 4:1 mux?

    hello every one can any one explain the implementation of 8:1 mux only using 2:1 mux Thanqs in Advance RGR
  12. R

    What is the difference between Logic Library and Link Library?

    hello every one can any one explain the main difference between the Logic Library and Link Library Thanqs in Advance RGR
  13. R

    What is the Well Continuity?

    Hello every one may i know the terms like Well Continuity P Well Continuity N Well Continuity Power Continuity Thanqs in Advance..... RGR
  14. R

    What is the Clock Latency,Network Latency,Source Latency,Insertion Delay?

    Hello Every one may i know the difference between 1.Clock Latency 2.Source Latency 3.Network Latency 4.Insertion Delay Thanqs in Advance......... RGR
  15. R

    What are non-ideal transistor characteristics in MOSFET?

    hello everyone can any one explain about non-ideal characteristics of a MOSFET Velocity Saturation? Mobility Degradation? Channel Length Modulation? Body Effect?
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