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Recent content by Reeyam

  1. R

    how to find area, latency, throughput, power in my design?

    T=(L/BW+R)∗H T : latency L : flits BW : the link bandwidth R: the routing delay per hop, (Hop is the basic communication action from switch to switch) H : the number of hops from the source to the destination node This is what I was looking for. Equation to find the latency. Thanks for...
  2. R

    how to find area, latency, throughput, power in my design?

    This is in the case of a normal network designed in hardware, not on the chip based VHDL After all thank you very much
  3. R

    [SOLVED] What do the terms marked in red mean in the timing report?

    Hi all, What do the terms marked in red mean in the timing report?
  4. R

    how to find area, latency, throughput, power in my design?

    the length of all packets is 25 bit my design not based buses my design network on chip 3x3 mesh based VHDL 5 master and 4 slave I want to find the specifications of the design in terms of latency, throughput, banwidth and Average energy
  5. R

    how to find area, latency, throughput, power in my design?

    This method is not useful in my design because the packet time I have varies from one packet to another The time between sending the packet and reaching the destination, for example 40ns means 4 clock because I have each clock = 10ns While another packet, time between sending and arriving takes...
  6. R

    how to find area, latency, throughput, power in my design?

    Ok, but how i can measure them ????
  7. R

    how to find area, latency, throughput, power in my design?

    thanks the time it takes (clocks) for the packet to arrive varies according to network congestion
  8. R

    how to find area, latency, throughput, power in my design?

    please Can you show me how to find them by architecture/code? or from simulation? i synthesize the code but no find latency or throughput
  9. R

    How compare between between mesh and torus?

    Hi all I designed network on chip, mesh topology and torus topology. output resulted correct in the two topology How do i compare between them? And Comparison is relative to what? (mean by calculations)
  10. R

    how to find area, latency, throughput, power in my design?

    very thanks But I did not find how to calculate the latency and throughput in my design Please if any one have information help me
  11. R

    how to find area, latency, throughput, power in my design?

    I have read it and have no details
  12. R

    how to find area, latency, throughput, power in my design?

    Hi, My project is design and implementation network on chip based VHDL I used Xilinx ISE and Synthesizing but i don't know how to find (area, latency, throughput, power) of the design I get the information in report (design summary, timing summary) in attachment. So what is meant memory usage...
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