Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If dont know, why do you respond? Dont you think the replies would be watched by many people, and your junk answered mail disturb others too.
think of the answer that you gave for a query.
clock setup and hold analysis
Hi,
We can overcome the set-up time, as discussed by other friends, by slowing down the Clock (10.2ns).
There is no way the existing Hardware work by changing the clock frequency!!! The only way to add additional hardware to the existing. If you do not want the...
Re: Running condition
It can be either xmit_ShiftRegH or xmitDataSelH or both. If any of these conditions exist then the statements with in the always block will be executed.
some question about ASIC
General Differences are,
1) TimeToMarket for ASIC is more.
2) We can achieve less i/o delay with ASIC.
3) FPGA time to market is less.
4) FPGA has fixed i/o delay.
thanks,
reddy
Running condition
First thing is your question is not elaborate,....,
always@( sensitivity_list),....,which you wrote is used to run always for a change in the reg/wire specified in the sensitivity list.
If you want to run for a repetitive period, then use a clock, which should be mentioned as...
In both the cases you should use Blocking, as it is combinational implememtation.
As per your doubt, in Case1, a=1 and b!=1. In this case, b can have x/z. So, you are always c=d. But in Case2, you are externally checking for b to be equal to 0. This definitely makes difference.
You try out the...
In both the cases you should use Blocking, as it is combinational implememtation.
As per your doubt, in Case1, a=1 and b!=1. In this case, b can have x/z. So, you are always c=d. But in Case2, you are externally checking for b to be equal to 0. This definitely makes difference.
You try out the...
Hello Ahsan,
Yes, You can not do the direct Decimal Multiplication in VHDL.
There are Two alternates for you,
1) You need to use functions to convert from Decimal to Bit type and then follow the algorithms, I dont know what algorithms u use.
2) You need to follow the IEEE representation...
Verilog HDL
Hello,
Check out these two links, it will be definitely usefule for you.
**broken link removed**
http://www.deeps.org/hdl_models/index.html
If you want to buy some books,...,
for the biginner,
VerilogPrimer - J.Bhaskar
VerilogSynthesis - J.Bhaskar
These two are good ones for...
how maximum frequency depends on setup time?
I heard that the hold time does not depend on the frequency of operation. Is this right. If so, how could we overcome the hold time violation?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
