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Recent content by realtek

  1. R

    Need solutions for data transfer problem in USB

    U$B Problem? for some reason I need to add a circuit that can transfer UTM1 8bits@60MHz signal to 16 bits@30MHz.but I dont know how to do this? here is my question , hope some u$b master guy can help me! Q1 : From UTM1 Can I just use 60MHz clk sample txval,txvalh and rxval, rxact...
  2. R

    SPI communication between a TMS320DM6437 and an ARM9

    Re: SPI communication Hi : try to visit www.m@cronix.com (@->a) and request SPI ROM sample I think they would like to help you (say you are a student)!
  3. R

    [HELP] Full digital DLL or DDR needed

    [HELP] Full digital DLL I need a full digital DLL for DDR Is there any experience designer can give some comments or reference papers ! Tks a lot in advance!
  4. R

    CUP - circuit under pad

    in during floorplanning? you can take CUP as a normal IO PAD ! ( read the .lef for placement)
  5. R

    What are the different ways of creating delays in a design?

    Delay in a design using delay cell that provide by foundary dont use inv for delay bacause you cannot control the delay time
  6. R

    interface between fpga kit and sensor with i2c

    using hdl write a i2c controller you can find i2c spec in g00gle then assign pin ( clk , sdata) , the connect to sensor
  7. R

    $fsdbDumpfile problem

    $fsdbdumpfile Procedure for dump fsdb use ModelSim(winnt , verilog) 1.install Modelsim 2.install Debussy 3. //add fsdb PLI in your testbench initial begin $fsdbDumpfile("pattern.fsdb"; $fsdbDumpvar(0,pattern); end 4. copy debussy/share/pli/modelsim/novas.dll copy...
  8. R

    FSM gate_level simulation problem

    use waveform view tools (verdi...) debug first find the problem is better then guess !
  9. R

    encyclopedia of electronic circuits

    insectronics download not best but worth to read (my opinion) Hans
  10. R

    What is the most important to study analog IC desigh?

    Gray and Mayer is also a good textbook (though it's focus on BJT) and you can find it in ED@boa... for "play" issue try download some example **broken link removed** mixer for simulation and play!
  11. R

    What is a function of PLL and DLL in FPGA ??

    difference between pll and dll + fpga Depend on your system need a clear clock source or not if you working on High-Frequency(> 68 or 100M) and it's a sync-system( ex: Sonet....) you need a PLL (select Altera 20Kxxx or above) if not ( some system use RC is enough), you dont need a PLL.
  12. R

    Can we synthesize ADC and RAM in DC?

    as you say it's hard macro DC is a compiler to compile your RTL to netlist In my opinion yout must set dont touch for these hard-macro when use DC synthesis!!
  13. R

    how can i build a platform to practising verilog or vhdl

    for new guy just want to do practice I suggest 1.use $ynplify to view thw synthesis result(PC base). 2.use Model$im to simulation (PC base). 3.read sold (Verilog/Vhdl) part.
  14. R

    synthesis for a design - what info do I need?

    to start synthesis try use DV(design vision), 1.set library path( wireload, ...) 2.open design_vision 3.read file 4. select clock (for constrain) 5. constrain 6. compile the detail you can read SOLD! (design_vision tutorial)

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