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for some reason
I need to add a circuit that can transfer UTM1 8bits@60MHz signal to 16 bits@30MHz.but I dont know how to do this?
here is my question , hope some u$b master guy can help me!
Q1 : From UTM1
Can I just use 60MHz clk sample txval,txvalh and rxval, rxact...
Procedure for dump fsdb use ModelSim(winnt , verilog)
//add fsdb PLI in your testbench
4. copy debussy/share/pli/modelsim/novas.dll
difference between pll and dll + fpga
Depend on your system need a clear clock source or not
if you working on High-Frequency(> 68 or 100M)
and it's a sync-system( ex: Sonet....)
you need a PLL (select Altera 20Kxxx or above)
if not ( some system use RC is enough), you dont need a PLL.