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U$B Problem?
for some reason
I need to add a circuit that can transfer UTM1 8bits@60MHz signal to 16 bits@30MHz.but I dont know how to do this?
here is my question , hope some u$b master guy can help me!
Q1 : From UTM1
Can I just use 60MHz clk sample txval,txvalh and rxval, rxact...
Re: SPI communication
Hi :
try to visit www.m@cronix.com
(@->a)
and request SPI ROM sample
I think they would like to help you (say you are a student)!
[HELP] Full digital DLL
I need a full digital DLL for DDR
Is there any experience designer can give some comments or reference papers !
Tks a lot in advance!
$fsdbdumpfile
Procedure for dump fsdb use ModelSim(winnt , verilog)
1.install Modelsim
2.install Debussy
3.
//add fsdb PLI in your testbench
initial begin
$fsdbDumpfile("pattern.fsdb";
$fsdbDumpvar(0,pattern);
end
4. copy debussy/share/pli/modelsim/novas.dll
copy...
Gray and Mayer is also a good textbook
(though it's focus on BJT)
and you can find it in ED@boa...
for "play" issue
try download some example
**broken link removed**
mixer
for simulation and play!
difference between pll and dll + fpga
Depend on your system need a clear clock source or not
if you working on High-Frequency(> 68 or 100M)
and it's a sync-system( ex: Sonet....)
you need a PLL (select Altera 20Kxxx or above)
if not ( some system use RC is enough), you dont need a PLL.
as you say
it's hard macro
DC is a compiler to compile your RTL to netlist
In my opinion
yout must set dont touch for these hard-macro
when use DC synthesis!!
for new guy just want to do practice
I suggest
1.use $ynplify to view thw synthesis result(PC base).
2.use Model$im to simulation (PC base).
3.read sold (Verilog/Vhdl) part.
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