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Recent content by RBB

  1. RBB

    Does Cadence have a RTL checking software?

    Cadence has a similar tool. It's called HAL and is built into irun.
  2. RBB

    How to get power of a standard cell from library

    Depending upon how the library was characterized, the power data could(should) be in the Liberty models.
  3. RBB

    matlab number of operations

    Profile execution time for function - MATLAB
  4. RBB

    matlab number of operations

    You can try using the profiler.
  5. RBB

    PSK Eb/No Vs BER calculation

    I'm not sure what you're asking here, but isn't it fairly obvious... BER = 1/2*erfc(sqrt(10^(5/10)))
  6. RBB

    CNR Vs. SNR regarding satellite communication

    Or this... **broken link removed**
  7. RBB

    To increase MATLAB speed

    Have you used the profiler to determine where Matlab is spending most of its execution time? Do you have access to the parallel processing toolbox? Can you compile some portions of your model into MEX?
  8. RBB

    Compile directtive and conditional instantiation

    What you are trying to do is possible, but not the way your approaching it. The problem with your code is the `define A (SEL==1'b0) & `ifdef statements are evaluated during compile time and not run time. I'd recommend using parameters & generate statements.
  9. RBB

    DSP System Toolbox matlab library

    Are you just going to keep asking over & over till you get the answer you'd like? Mathworks has this thing called licensing, so if you don't have a valid license you won't be able to utilize the toolbox. In short, if you need it that bad, go buy it.
  10. RBB

    FPGA: 2 ^ X, how do you do it?

    My initial thoughts are to divide x down by 2 until it is on the range of [0, 1]. So you're computing y = (2^n)^m, where x = m*n and m is a power of 2, and n is on the range of [0, 1]. You can then do a LUT or a linear interpolation to compute v = 2^n. Take v and multiply it by itself m...
  11. RBB

    To make netlist have the same reg names as those in verilog code

    Tried it with both 2008.09-SP1 & 2010.03-SP4 with no errors. ---------- Post added at 18:47 ---------- Previous post was at 18:14 ---------- I looked into it & it's because your internal signal names really don't do anything. They just get pseudo-buffered via the assign statements, so DC is...
  12. RBB

    To make netlist have the same reg names as those in verilog code

    No idea. This has always worked for me in the past, so it's either a version issue or a configuration issue. I'd recommend searching on SolvNet.
  13. RBB

    To make netlist have the same reg names as those in verilog code

    Instead of using read_verilog try: analyze -format verilog blah.v elaborate blah -update
  14. RBB

    To make netlist have the same reg names as those in verilog code

    This has worked for me in the past, but I haven't tried it lately or with the latest version of Design Compiler. I'm assuming you're using Design Compiler. Try placing this in your RTL: // synopsys dc_script_begin // set_dont_touch mem_read_data_r // set_dont_touch mem_read_data_valid_r //...
  15. RBB

    reg wire difference in combinational circuit...

    Not necessarily. In the link in the first post it shows two code snippets: one coded with reg & one coded with wire, but both produce the same behavior. In that case it really comes down to coding style; preference and/or readability on which one to use. Also you may see a slight simulator...

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