Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Razob

  1. R

    Package delay (or flight time) calculation using IBIS

    I need to know the flight time (or trace length) of one of IC. But I have only IBIS model. I think I need to make any simulations to calculate flight time. I am able to use Hyperlynx by Mentor or Sigrity by Cadence to do this. Could someone provide to me any instuctions how I can implement this...
  2. R

    SSTL VIH(ac) levels according to DDR3 SDRAM

    Hello, everybody! I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels. Timing specification for DDR3-1066 SDRAM normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135. Which one of all levels I should use in my timing budget calculation? Levels are...

Part and Inventory Search

Back
Top