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Ok. So, that means there should be any gap between the last functional pad and the corner pad?
This would then also apply for the first pad, which should then be placed with offset=0.
Am I understanding you correctly?
Cheers,
Robert
Hi,
I am using the MMMC-flow of Cadence Innovus. Hereby, I set the IO placement file and then initialize the design using the command init_design.
My IO file looks like the following:
(globals
version = 3
io_order = default
)
(iopad
(topleft
(inst name="PADS/CORNER_NW"...
Hi,
I am trying to perform a post-synthesis simulation.
For synthesis, I am using Cadence RTL Compiler 14.2and my target technology is UMC 65nm.
To perform the simulation, I write out the SDF file after finishing synthesis and then back-annotate my synthesis netlist with it.
Creating the SDF...
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