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constant gm bias start up
As srivastsan told you , if you are into a stable point , as is usual with gm constant circuit ,you can do what do you want but if is point is stable (and current equal to zero is a stable point), your circuit won't work properly in silicon.
Start up circuit is...
SS, TT, FF corner
Worst case usually depends only on what you are doing, sometimes worst case is FF , and sometimes with SS or SF or FS .It depends of the circuit... unfortunetly there is no rules for that.
I don't agree with you steer , Analog designer comes better with time.And I'm not sure 10 years ago lot of people worked at 5 volts (maybe 15 years ago yes).
B.Gilbert is one of better designer in the world and sure you can learn a lot reading stuff from hin , published 10 or 20 years ago.
increase phase margin
First what do you need a gain of 121 dB?
Because big gain ----> stability hard!
If your circuit have got a Miller capacitance you need to increase Miller capacitance value.
Re: Dummy connection
For me your problem comes from ESD problem, problably you are working into a I/O team.
So normaly you don't have the right to connect a Gate directly to VDD or VSS without ESD protection.
But in your case you don't care about this problem , I guess , but you need to check...
plot gm cadence
Hello Blue2lucy ,
I will try tomorrow what you said.
If I have well understood ,I need to perform a sweep DC analysis , and saving all.
I use spectre , I will try it tomorrow .
spectre gm id
Hum ,never I did do this simulation but I guess this is not the right way.
I give you an example , how you perform the analysis of gm in case rail to rail input amlifier ?
,because constant gm play a big role in a such amplifier
The best way to know your PSRR of your circuit is to perfprm AC analysis as wee_liang told you AC=1.
But you need to perform this AC analysis for the both supply (i.e VDD and the ground) ,so two different analysis
Sorry I don't think so Golbaidh's circuit is wrong.
I give you an example PNP1 emitter is connected to the Base that is wrong , the right answer is Base connected to the ground.Second point Bandgap's PMOS,the upper one has got PMOS gate connection is wrong.I hope this will help
Re: Common centroid
Well I give you my feeling on this topic
M1-M2 common centroid , minimun lengh +0.01u or +0.02u (depending if is odd/even pitch) but big W because area play (mitsmatch in Vt) a big role and of course because the bandwith depend of the gm of these transistors too.
M3-M4...
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