Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
The original idea is to use same size nmos pair and different size pmos pair. The right-hand pmos should be stronger than the other one.
For the 1st order calculation (assume perfect saturation characteristic for both nmos and pmos, and vdd is higher than the min value which is required to...
You can check the model file to find out the max length value supported by the model. Usually it can be 10um, but you need check that.
If you need even longer, just simply connect more devices in series. Hope it helps.
Rui
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
