Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Ravindranit

  1. R

    Problem with declaring inout port in code

    Re: problem inout port thank you for your help.... i am also facing problem to write the test bsnch of the above code. it give me error on declaration of inout port type ( reg or wire). if i am taking reg it gives eroor " net is not a legal value". and when i take it as a wire it does take...
  2. R

    Problem with declaring inout port in code

    problem inout port Hello friends, I want to use inout declaration in my code. but it gives the error that port is not a legal value. i use it into the always block both as a input & output. code is: module check(a,s1,out,d,enable); input s1,enable; input a; output out; reg b; inout d; reg...

Part and Inventory Search

Back
Top