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Appreciate your reply. But it does not help at all except adding criticism. I did not intend to code this way. If was an accidental finding.Anyways, this is what i am thinking. If you can confirm that would be great.
count <=count+1; is a non-blocking assignment. If you have it in a for loop...
I have written a code for a multi bit shift register and there is a counter also in the same always_block for a different purpose.
logic [W-1:0] mem [N:0];
logic [W+1:0] sum_act,sum_fin;
logic [N+1:0] count;
always_ff @(posedge clk, negedge reset) begin
if(!reset)...
Hi,
Thanks for your reply. I am using only .options POST
And i tried running in steps of 100n as well which is taking almost the same time and giving the same message.
I did not use any .probe statement so that means it records all the values at all point of time?
Regards,
RC
Hi, I am trying to simulate the ADC i have designed using Hspice. I have a clock running at 20Mhz. i.e a period of 50 ns. I need the simulation to run till 100 milli seconds becuase i am using a current mirror ramp generator for generating a ramp vooltage which requires that much time for...
time: command terminated abnormally hspice
Hi, I am trying to simulate the ADC i have designed using Hspice. I have a clock running at 20Mhz. i.e a period of 50 ns. I need the simulation to run till 100 milli seconds becuase i am using a current mirror ramp generator for generating a ramp...
error happens when writing waveform for post
Hi, I am trying to simulate the ADC i have designed using Hspice. I have a clock running at 20Mhz. i.e a period of 50 ns. I need the simulation to run till 100 milli seconds becuase i am using a current mirror ramp generator for generating a ramp...
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