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Ok. I will look into that.
I kind of understood what can be done but still have a doubt in that.
Say am using a seed value of "0001" at the Txr lfsr. And say the value is received as "1001" at the Rxr due to channel distortions. This value (1001) is given as seed to the Rxr lfsr.
This seed...
The BERT counts the number of erroneous bits in the received data. If we try to match the rxd_data with the rxr_lfsr value to synchronize the two values, it means we are assuming that the first data rxd will not have error right?
Say I am using seed value as "0001" at the Txr. So I am using the...
Yes I can understand.
I want to use a single FPGA to act as a PRBS generator and as a BERT. The data is to be passed through optic fibre medium.
Txr PRBS generator(FPGA)-->DAC-->SMA Connector-->electrical amplifier-->fiber-->electrical amp-->ADC-->Rxr(FPGA).
library ieee;
use...
I have made all the changes. This code works in simulation. Any other chnages I have to make to make it work in hardware?
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------
entity lfsr4_txrrxr is
port (
rstN : in...
oh ok . I have included clk in the code and its working fine in simulation.
Will this work in the hardware too like how I wanted it to work?
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------
entity lfsr4_txrrxr is
port (...
Re: error while using for generate
When I simulated in model sim, the m and error values got incremented even without clk in the p3 sensitivity list. Clk is needed ?
Will this code work as a transmitter and error tester when loaded in a fpga?
Re: error while using for generate
Thanks. Will find out about FSM.
Will this code do the work I wanted to ?
When simulated in model sim, it gave proper values.
Instead of using components, I tried this:
-- A 4-bit Linear feedback shift-register (LFSR)-PRBS & BERT.
--
--...
Re: error while using for generate
Sorry I understand its difficult to help without giving proper inputs.
How do I attach my code ?I could not find syntax tags icon anywhere !
Here is the code of the two components. Basically I want to send a 4 bits from a 4 bit lfsr and receive the 4...
error while using "for generate"
I want to run the two components one after the other , for 15 times. the for generate is showing the following errors:
** Error: Nonresolved signal 'led' has multiple sources.
** Error: Nonresolved signal 'q_main' has multiple sources.
** Error: VHDL...
I have found out that the "JP3 Sense resistor for measuring the power consumed by the 2.5 V supply to VCCIO, the DDR, the flash I/O, and the SSRAM" has been shorted.
Also, "JP6 Sense resistor for measuring the power consumed by the 1.2 V
VCCINT supply to the Cyclone III device" has been...
Hi,
All the unused pins are configured to inputs tri-stated to weak pull-up . Besides I also tried burning a basic AND gate code, it had none unused pins. Even then the FPGA started to heat. Now even without loading any code, just switching on the board causes the FPGA to heat. So what are we...
Hi,
yes the board was working fine previously. Am working on interfacing a ADA_THDB board to my Cyclone 3 starter kit. The latest edition i did when it started to heat was adding a PLL to increase the clock frequency . MY fpga provides only 50MHZ , while the update rate of the DAC is 125MSPS ...
My cyclone 3 fpga is getting heated up very fast in a few seconds after switching on the power even before burning the code.
The adapter is working fine and so there is no problem with the power supply. What could be the reason for this unusual heating?
It got heated in a few seconds !
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