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In IC6
Go to - Options -> Dynamic Display
Turn on info balloon, select desired info, apply, hover cursor over path.
It should then display the path length
How you put in the number of fingers in the schematic may effect your simulations. A transistor with a width of 1000u, mult of 1 is different then a 1000u transistor with a mult of 10 which if different then a transistor that has a width of 100 but iterated <1:10>.
Any NWELL you have connected like this will get flagged due to potential latch-up issues. Be sure to ring the NWELL with a PSUB contact ring. Also, try to keep these NWELLs as far away from ESD devices that you can.
Why have a NWELL with nothing inside of it? The assumption is that a device will be inside the nwell. So, all nwell will need to be connected to some potential.
Not sure this is correct. Assuming this is a simple mos device then the connections are S/D(gate) on left or right, GATE(Drain) on top, body(Source) on bottom.
The charge build up may not be from the gate to body of the mosfet. It can also be the body to gate of a mosfet. So during processing, before contact and metal, there can be a charge build up on the body of a pmos transistor (nwell) relative to the gate. This is process dependent as anilkrpandey...
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