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Hello, All
I am trying to understand some concepts about Embedded Linux and Why engineers use it.
I read this article
https://www.eetimes.com/document.asp?doc_id=1277902#
and I understand that applications that need server controlling and image processing
Is there the only applications for...
Hello, All
I am trying to understand some concepts about Embedded Linux and Why engineers use it.
I read this article
www.eetimes.com/document.asp?doc_id=1277902
and I understand that applications that need server controlling and image processing
Is there the only applications for Embedded...
Hello, all!
I am new in UVM and I have this error while compiling my design
Could not find the package (design_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the...
Hello, all!
I am working on top design module on Questa. The code is like
module top(
input wire ..
output reg ..);
reg..;
wire..;
When I run the simulation, It shows me the wires and registers defined between the brackets but registers and wires defined outside the module are not shown.
And...
Hello, FvM!
In the first image, "enable" signal was = 1. So sda = sda_reg and that works
In the second image, "enable" signal was = 1. sda should = sda_reg but this is not happening
When "enable" =0, the master will read from the slave (acknowledge bit)
I managed this piece in my code, but I...
Hello!
I am new in verilog and I begin working on I2C protocol hardware implementation
The master code works well
but when I combine all files together the master code does not work as it was
"sda_reg" is the problem and I do not know what I did wrong
the top code
module top;
wire...
I got this fatal in simulation at this line A.KeyExpansion(); in TEST.sv file
TEST.sv file
import uvm_pkg::*;
`include "uvm_macros.svh"
import code_pkg::*;
module test();
AES_do A;
int i;
initial
begin
A.nonce [8 ]={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
A.key [16]={...
AES_MoniterAFter.sv file's job is to import a C code and predict the output. AES_test is in top module(the interfacing module between UVVM files and verilog code). I already compiled the top module.
- - - Updated - - -
I found my problem. I declared two variables with the same name + "r" in...
Hello!
I am trying to run my first UVM design using these command but I get those errors
And the commands(these commands used after compiling the design file and UVM files)
vlog AES_MoniterAFter.sv -dpiheader dpiheader.h add.c
vsim -coverage -t 10ns -novopt work.AES_tb_top...
Hello!
I want to concatenate 2 unsigned char (temp and counter) contain hexadecimal numbers and store them in another variable (after) but this code ives me segmentation fault. Could someone help me?
Thanks..
#include<stdio.h>
void concat()
{
//unsigned char state[4][4];
unsigned char...
I added a schematic file to my project and selected "View HDL Functional Model" option from design menu and it gives me (schematic file name.vhf) file and that is what written inside it and the schematic file is empty.
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