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Recent content by RamyRady_RF

  1. R

    cadence error running verilogA (SPECTRE-18): Segmentation fault.

    it is indep. of the code, even a cap from ahdLib, or any other veriloga cell
  2. R

    cadence error running verilogA (SPECTRE-18): Segmentation fault.

    Hello, I was trying to rerun the same verilogA code again, but I face this error: any suggestions? Thanks
  3. R

    Modeling 5th order CTSD in VerilogA

    I am Modeling the 5th order CT SD with feedforward architecture, I couldn't find a similar model in cadence libararies so I implemented my model. However I am not sure how accurate it is I used Sum, loopfilter laplace_nd() of the transfer function I got from matlab and then ADC and DAC.
  4. R

    DAC Jitter Modeling for CTSD Modulator

    Hi, Do you know How to add mismatch to the DAC Model that calculates the value each clock? Thanks
  5. R

    Modeling 5th order CTSD in VerilogA

    Hello, I am trying to model a 5th order CT Sigma delta modulator in VerilogA, Are there any simple way to implement the transfer function that just derived from simulink as a verilogA model? I mean H(S) directly as a verilogA model?
  6. R

    DAC Jitter Modeling for CTSD Modulator

    Since, I am new to verilogA, could you tell me How to model Clock with jitter?
  7. R

    DAC Jitter Modeling for CTSD Modulator

    Hello, I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?
  8. R

    Resources to learn about silicon photonics IC design

    Hello, I would like to ask about the best resources to learn about silicon photonics (PIC) IC Design. Please feel free to recommend me books, courses, paper or upload any useful materials. Thanks
  9. R

    Resources to learn about mmwave IC design

    Hello, I would like to ask about the best resources to learn about mm-wave IC Design, both integrated or discrete. Please feel free to recommend me books, courses, paper or upload any useful materials. Thanks
  10. R

    Switched-capacitor latched comparator simulation question

    How to simulate the Regeneration time constant and the Dynamic gain?
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