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am going to design a programmable divider it includes prescalar(P), main counter(M) and swallow counter(S). i need to clarify what are the values we need to give for P,M and S (ratio).
is there any possible to give analog input in MODELSIM. i need to design analog vco using verilog. i wrote transistor level coding , but its not working. please guide me how to proceed.
Re: i got an fatal error" Too many port connections. Expected 2, found 3"
yes, divides.v is the name of the compiled file
divi1 is the module name of compiled file divides.v
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when i simulated the nand gate without buffer code ,i got loaded.
after adding the...
i tried to compile a verilog code for divided by2 circuit using flip flop , its needs a feedback so i used a buffer at the output, the code got successful compilation but while loading i got this error
# Loading work.my_buf
# ** Fatal: (vsim-3365) C:/altera/10.0/divdes.v(7): Too many port...
in the design of a PLL ,i have planned to add additional transistors in it. is it possible to implement this additional transistor as code in modelsim.
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