Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ramkumara

  1. R

    2 stage interpolated fir filter with pass band gain of 6.02 db

    Hi all, I am designing a interpolated fir filter. I have designed FIR filter using the coefficients that I got from matlab. But how to design a 2 stage interpolated fir filter with pass-band gain of 6.02 db. I read many IFIR filters which uses linear interpolation/b spline interpolation. But...
  2. R

    standard cell height and width

    Hi all, In standard cell, always height is kept constant and width is varied, What parameter of the transistor in schematic entry is making this width to vary. Also if I want to change my height of the cell, what should i do?
  3. R

    Why does this array indexing not work in verilog?

    ya, change the index range, it will work....
  4. R

    How to initialize an array structure in verilog?

    k, for 1st locatioin, how to initialize all the memory locations.....

Part and Inventory Search

Back
Top