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Recent content by ramkka

  1. R

    [SOLVED] What is via stacking?

    Vias directly above on one another are called as stacked vias. For yield purpose there will be limit in tech file.
  2. R

    Difference between Via and Cut??

    Via can have more than one cut, multi cut vias will be good for yield.
  3. R

    library for lower technologies

    @rca >> The CCS and NLDM describe the timeplate with list of point to allow the backend tool to reconstruct the waveform. could you please explain in detail??? Thanks,
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    [SOLVED] Creating Milkyway library with macro .lef file

    LEF generally read by cadence tools. FRAM is the LEF equivalent in Synopsys tools.
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    What are the details about level shifter and isolation cells

    Re: Details about level shifter and isolation cells Isolation cells are generally inserted in POWER ON domain than OFF domain, to prevent the don't cares coming into the ON block.
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    [STA] Hold violation doubt

    If you are a physical design engineer, you may consider to reorder the scan chains to get the minimum skew between the flops.
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    Couple of quick questions on shielded wires

    Hi jktstance, This is a very interesting question. My opinion is : The slow down of signal happens when there is opposite swithing on the nets which have cross coupling. Now you are isolating the two nets by shielding that means the effective cross coupling that introduces slow down is less...
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    What is the use of adding filler cells to a design?

    Is there any limitation for decap cells in design? Is it related to package inductance? Ramkka.
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    [SOLVED] Question about the IC compiler

    Use route_guide, and please check if there is physical connectivity for VSS and VDD of std cells.
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    Possible Reasons Routing Congestion

    What could be the reason for hot-spot congestion on low-pin density area?
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    [SOLVED] What is an RDL layer and what is the importance of it?

    Please let me know.
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    How to do gate level simultaion under on chip variation analysis mode ?

    HI, with OCV setup : launch delayed and capture made faster Hold: Launch is faster and capture delayed. Thanks, ramkka
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    what we call if a gate output is given feedback to input ,combo are sequential?

    Hi, My basic understanding of sequential is that it works with edge sensitive. Combo is not. Please correct me if I am wrong. Thanks, Ramesh
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    Decap Cells & Filler cells

    I didn't understand the even odd layers statement.
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    scan reordering and scan stitching

    scan reorder doesn't change the cells placement but it will reconnect the Q-> SI pins according to the reorder.
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