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When I use calibre to extract the circuit (with CC+C option) - I see a big intrinsic cap (close to 300fF) for a pmos bias node (biasp to VSS) . The CC between biasp to VSS node is negligible (<<0.1fF) . My question, usually the pmos bias node parasitics should be referenced to VDD (nwell...
Hi jecyhale,
Can you give the relationship(equation) how did you arrive @ GBW of opamp for the requirement ?
Or we should just rely on verilog-a modeling of opamp (with arbitary min GBW to start with) and observe the pole frequency changes, and change the GBW (to finally arrive @ sweet spot)...
Re: Op-Amp Design
Hi Wang,
Try this
" Analysis and Design of Analog Integrated circuits" - Fourth Edition by Grey/hurst/lewis/meyer
It has got some sections devoted for Fully Differential Opamps, CMFB etc.
I found it very useful!!
Regards,
Ramesh
There are two things you should be concerned abt.
1) The GBW of opamp affects the pole/zero frequencies (arise from the filter).
You could model the opamp as verilogA (include GBW parameter in verilog-A) and simulate the filter characteristics (with verilog-A opamp)
and chose the GBW - which...
filter and op-amp bandwidth
To determine the GBW, the loop gain (Aol) has to be maintained @ highest frequency of the input signal (w= 20 MHz).
Aol = GBW/w
For example, your open loop gain requirement = 46 dB (~200)
Then your GBW > Aol* w
GBW >...
Hi,
I am trying to estimate the drain resistance of a transistor (due to the increased clearance (~5um) of drain contacts to the poly) to model it in my simulation.
My transistor size is 5 X (W=30um, L=0.5um)
I want to know how should I go with estimation of W,L for the resistance for the...
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