Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
We use shared(.so) files instead of compiling .cpp files everytime.
Similarly, can we use .so files for some verilog modules which we do not change frequently?
Thnks
noimmedca switch for Questasim
Hi all,
Can anyone give example usage for "-noimmedca" switch for Questasim. I referred tool docs for this switch but I could not find any example..
thank you
what about the clock skew at the flop inputs?
if the flops are getting clock at different time instances, outputs of flops also changes at different time instances(which can cause glitch)
please correct me if i am wrong..
Hi
Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'...
Hi,
you can get UPF documentation from the following link
http://www.accellera.org/activities/p1801_upf
for upf topics:
http://synopsysoc.org/magicbluesmoke/
Re: ESL and Verification
Hi thank you for your reply
my question is
if
1.ESL to RTL(using some tool) is possible
2.formal verification between esl and rtl is also possible..
then functional verification will happen at ESL level by the designer(not at RTL level).
That means.. there will not be...
These days High Level Synthesis tools (Mentor's Catapult,Synfora's Pico for C/C++ to RTL) getting into industry.
Will there be any effect of these tools on functional verification using VMM/OVM? (atleast in near future..)
Please correct me if my question itself is wrong...
Thank you for your reply.
I feel we need precision only for the post layout simulations with SDF annotation(Please correct me if i am wrong).
Are there any other situations in which precision is important ?
What factors we must consider while selecting the timescale for simulation?
Thank you..
design for corner cases
i am new to analog design. i want to design a circuit which works at all corners. i am designing circuit with some margin ( design amplifier for 60db gain, if the spec is 50dB). Is there any way to decide the optimum margin for a spec based on the technology and circuit...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.