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Recent content by ram a

  1. R

    [SOLVED] plzz help me debug this verilog code of simple microprocessor........................

    module AC ( input [15:0] data_in, input load, clk, output reg [15:0] data_out ); always @( posedge clk or negedge clk ) if( load ) data_out <= data_in; endmodule module ALU_REG ( input [15:0] data_in,input clk, output reg [15:0] data_out ); always @( posedge clk or negedge clk ) data_out <=...
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