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Recent content by rali

  1. R

    configurable block rom using vhdl

    rom en vhdl i wanted to have a reconfigurable rom, the read width and depth may be non standard sizes and are required to be changed so that the component using the rom can be tested for performance using different wordlengths. actually there are many sizes of arrays to be read depending on...
  2. R

    configurable block rom using vhdl

    vhdl generate statement ram thanks very much guys for your help.i'm not using xilinx core gen.i'm writing the vhdl code for the rom for now.
  3. R

    configurable block rom using vhdl

    vhdl using generate thanks for the replies. i too thought the core gen blocks need the width and depth fixed.So to have a generic rom i'll have to write a vhdl code for the rom? could anyone please guide me how to infer block rom.
  4. R

    configurable block rom using vhdl

    generic rom vhdl code hi, i want to implement a block rom with generic read width and read depth in vhdl.i'm using modelsim se.Can xilinx core gen block rom be used to have the generic read width and depth or should a vhdl code be written to infer block rom.The design is to be synthesized...
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