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Hello I am simulating Tunnel FETs in sdevice. My drain currents are extremely low (1e-7), I want in order of 1e-5.
Please help how can i increase.
Thanks
Rajat
Hi,
I am simulating a TFET, drain currents are extremely low (in order of 1e-7). I want to increase it to 1e-5 atleast.
I am using sdevice.
Somebody please help.
Thanks
Rajat
HI,
Can anyone please tell me what should be the size of the Mosfet to allow a safe conduction of a particular drain current? in cadence GPDK 180nm?
i.e What is the criterion to select the width of the MOS for a particular current? I mean what is the safe size to sustain a current (say 1uA)...
Hello,
This is a good explanation erikl. But I am not really convinced for the question i have in mind.
"Is it possible to have a MOS in Sat region with VGS = 1.5V, Vth=.5 and VDS = 0.67V??" This circuit is simulated in Cadence composer schematic 0.18um Tech. The simulator says its in SAT. As...
Re: LabView
LABVIEW is a platform and development environment for a visual programming language from National Instruments. The purpose of such programming is automating the usage of processing and measuring equipment in any laboratory setup.
hi friends
i am rajat, very new to the TMS320c6713 processor,
can any one of you please tell me how can i burn the program in to the board through PC? i have licensed CCS V4, but dont know how to program it.
i am doing the project huffman encoder,
Please help me
hi friends, i got to know that there are many architectures are existing for xor gate out of those i know only one, ie AOI(and or not)
can anyone please introduce some other arch for xor to me
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