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Recent content by raiotek

  1. R

    Verilog - ignored specified memory location

    Do you mean you just want to write a pattern(testbench) to test the MEM READ/WT? if yes, at this pattern, the RAM for you is only a model,you can add a if~else statement in this model to restrict write to address (0010),(it's only a model, so physical error is not importment, what you want to...

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