Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by rahulrc

  1. R

    Hold fix issue - hold violation problem

    Re: Hold fix issue Thanks xinsu & praneshcn, I checked the data_path and there is only one buf in the data_path. i will reconfirm the sdc input delay constraint. Regards.
  2. R

    Hold fix issue - hold violation problem

    Hold fix issue Hi All, i am having issue in doing hold fix. the path is input to register path. hold violation is -0.640ns. and hold margin is 0.410ns. can anyone guide me how to fix this? Thanks in advance.
  3. R

    post the pros and cons of these timing analysis tools

    Re: ETS vs PT very open ended Q...
  4. R

    captable file in encounter

    Hi all, i am new to soce. what is captable file? where it is being used? any document on format of captable? Thanks in advance.
  5. R

    Extended_cap_table section of captable file

    Hi all, what does the extended_cap_table section in captable file represents? (':cry:') thanks in advance.
See more

Part and Inventory Search

Back
Top