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Recent content by rahul99_spil

  1. R

    Help me design a combinational circuit

    Hi All, Design a combinational circuit that gives a active high signal whenever the input is perfect square..and also please provide vhdl logic also Thanks Rahul
  2. R

    Cypress cpld configuration

    Hi we have the configure the cpld dynamically by sensing the I/O pin of pin.Is it possible on cpld??.If it is possible how it can be done.. Thanks and Regards rahul
  3. R

    pipeline delay, how to implememnt the pipeline delay in vhdl

    pipeline delay hi what is pipeline delay.. how to implememnt the pipeline delay in vhdl.. thanks rahul
  4. R

    Sync signal on green data

    Hi we are trying to implement ramdac in fpga.In ramdac sync signals are placeing on the green data. Is their any specfic reason to implement like that. thank you
  5. R

    Implemenration of RAMDAC in FPGA

    yes we are going to use the DAC'S externally... and remaing things we have to implement in FPGA
  6. R

    Implemenration of RAMDAC in FPGA

    Hi i would like to implement the ramdac operation in fpga. Can any body send information about this thing,.. regards rahul
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