Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi Kumar,
Thanks for reply.
No congestion between the macros.
In design i have seen lot of congestion in standard cell logic area. Especially in cpu1 and cpu2 modules. Each module consist of 260 k instances.
In module, lot of detoure connections. Cell density is almost 70 to 80 % range. I...
Hi kumar,
Thanks for reply.
Now placement optimization(preCTS) run is going on. I have observed the log file, its look as more H and V congestion.
Can you suggest macro overhead area and standard cell overhead area , and also core area based on my design?
Suggested by you, shall i take core...
Hi,
My design consist of 166 macros and 650k instances(40nm,TSMC, 6 metal layers). Macros vs logic occupied area ratio is 85%:15%
std cell area:807358.653um2
macro area : 4580736.839um2
We don't have spec for the block area.I need to start with cell density with 60%. And we have to decide...
Hi sir,
i have attached my base paper.Please go through Figure (3). Can you please tell me the approximate Constant Gm Bias Circuit. So that i can attach to my proposed LDO ie.Figure (3). I can design with W and L values,if you give the circuit schematic.
Thanq..
Hi sir, i have designed LDO with regulated voltage 2.5V with supply 3V. I sweep 2.7V to 4V and did DC analysis(without load condition) ,the output value is incresing from 2.5 to 2.582. At input 2.7V, output is 2.5V and input 4V, output is 2.58V. How can i regulate the design properly?
Thanq,
Hi sir, i have designed LDO with 100mA load. I have 90dB gain and 110degree phase margin. When i checked without load(0 mA) i got 65dB and poor phase margin 6degree. I could't find whats the problem.
Hi sir,
In LDO design i have used reference voltage as DC voltage source(1.25v),instead of design bandgap circuit.Will my design properly work at typical conditions?
---------- Post added at 17:40 ---------- Previous post was at 17:25 ----------
Hi sir,
1)How i will get conclude...
Hi sir,
I have designed LDO with supply 3v.
Does't work my design with supply 3v when the load 100mA??
Iam using 180nm CMOS Technology,how much supply is sufficient for driving
100mA load?(Need to regulate 1.8v and dropout is 150mV).In DC analysis i sweep from 2v to 4v.
I already...
hi sir, i have designed LDO.Target with 100mA load current.But i have reached up to 25mA.I could't able to drive more load.My opamp gain is 80dB.70 degrees phase shift.Using 180nm CMOS technology.I could't find what's the problem.Constant Gm Bias circuit designed with input current 1.2uA.I...
Hi sir ,there is a small doubt on MOSFET,0.35um CMOS technology:
1)what is the result value should be for [Vgs-Vds]?(if it is N-MOS)
2)Number of P-MOS 4 terminal devices connected in series , all substrate of mosfets needs to short with source or Vdd? How it will effect?Which one is prefarable...
hi sir,
1)what is the advantage to use inductor based feed back in LDO?will it to DC voltage while doing AC analysis?
2)In design some MOSFETs scaled with exact 0.35um length and some MOSFETs scaled with multiple of 0.35um.How it will effect to our design?(iam using 0.35 CMOS technology)
Thanq
Hi sir,
In my base paper (Fig3) i need to generate 2.5v Reference voltage and bias voltages Vb1,Vb2,Vb3,Vb4 and Vb5. Shall i use DC voltage source with corresponding values or i need to generate the circuits?
Do you have any idea about how to analyze bias voltages for particular value.
Thanq
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
