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Recent content by raghava216

  1. R

    Real to decimal number conversion in VHDL

    @rca These numbers are generated by the testbench. @FvM passing that real number as an argument to IEEE TEXTIO package write() prints the number in scientific notation, which is not what I want to see. would u mind to post the exact VHDL code?
  2. R

    Real to decimal number conversion in VHDL

    ya.. its part of a test bench
  3. R

    Real to decimal number conversion in VHDL

    I have some real numbers like 9.123472e+002. I need to print these to a file after converting them to normal decimal number representation from scientific representation like in this example I want to write 912.3472 to the file instead of writing 9.123472e+002. Any idea how to do this in VHDL...
  4. R

    DAC driving ISO124 and MUX

    Hi I am working on a design where a DAC needs to drive an isolation amplifier as well as a MUX. The output of the MUX goes to an ADC. I wish to determine if the DAC can really drive those two devices properly or do I need a buffer or some other intermediate component. The components here are...
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    Convert IEEE754 single precision number to 16-bit integer

    Dear All, I would like to convert IEEE754 single precision number to a 16-bit integer (2's complement representation). I read that there is a command 'int16', but it is not accepting the hexadecimal string as input argument. Also, the output 16-bit integer should be represented in hex. For...
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    Need LCD Controller (SED 1330) C simulator

    Hi all I need a C/C++ code for LCD controller SED 1330F i.e. I need Simulator for SED 1330F.... If anyone has it, please share or inform where it shall be available..? Thanks
  7. R

    WLF Error in modelsim

    I just did a simulation in modelsim 6.0 SE and after the simulation, I opened the 'vsim.wlf' file. It did not open and threw the following message. I am not able to open the waveform even after closing the existing instance of modelsim and opening in a new one. This is the error message:
  8. R

    [Moved] user defined data types in verilog

    I want to know how to define user defined data type in verilog? I want to define a two-dimensional array with a name say 'memory' and I want to declare a new variable of type 'memory' and assign values to it... How to do this? Plz. help
  9. R

    wait statement usage in vhdl

    what is the difference between the two approaches? 1) process(a,b) begin ---- end process; 2) process begin wait on a,b; --- end process;
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    help me optimize this VHDL to verilog conversion

    @FvM Thanks for ur reply. You are right in saying that . But, in the always block, there is only a single if-else, so I guess it won't effect much if its concurrent or sequential. May be that is why you said . But I did not get how it would mean different kinds of behavioral description. That...
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    help me optimize this VHDL to verilog conversion

    @rca I work with both the HDLs. I am interested to know the equivalents in both to improve my understanding.
  12. R

    help me optimize this VHDL to verilog conversion

    Hi.. I want to know the best way of converting the below VHDL code to verilog code First type of VHDL code: a0_n <= a_i(0) WHEN d_en_i = '1' AND dat_en_i= '1' ELSE '1' WHEN d_en_i = '1' ELSE 'Z'; There are two ways I can think of writing this...
  13. R

    compatibility problem in Questasim 6.4c

    Hi! I wrote a controller design in vhdl and tested it with a script based test bench in Modelsim 6.0 SE. When I run the test case 1, it got successfully executed and generated the required report files. When the simulation is run in modelsim 6.0 SE for the first time ( irrespective of...
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    component instantiation query in verilog

    I wrote "comp X(.a({b,a}), .b(c));" in my code. I am not able to see to bit level like a[0] is mapped to what and a[1] is mapped to what. But, On placing mouse pointer on the signal a(1:0), it displays "Input pin: a(1:0) => Signal b,a" in RTL view. I am using Xilinx 12.2 ISE. So, I feel comp...
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    component instantiation query in verilog

    Yes Got it. The inputs need to be concatenated. But how is the order taken? In the above example, I want to map a to a[0] and b to a[1]. Which is correct? comp X (.a({b,a}), .b(c)); OR comp X(.a({a,b}), .b(c));
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