Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi everyone,
I am doing P&R for a design and would like to use some specified cells (bufs/invs) to add into the path with hold violations. However, I am not sure how to implement this? Can anyone give me some suggestions?
Thanks a lot,
Tom
Hey, guys,
I have written a tcl script to drive DC to uniquify a design. But I always get an error said:
Error: File is not a DB file. (DB-1).
How to solve this problem? Can anyone help me?
Thanks.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
