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Recent content by r_a_c_a_4_u

  1. r_a_c_a_4_u

    Recommend me a high level synthesis tools for FPGA

    looking for advice! i dont think there is a single tool ...i think mathworks and xilinx have monopoly in these area .... so you cant help ... you will have to buy those products ..
  2. r_a_c_a_4_u

    Recommend me a high level synthesis tools for FPGA

    looking for advice! you have to buy the softwares .... and there are a lot of compatibility issues of the versions of different softwares ... if u are using sysgen 7.1 you need a MATLAB R14 or R14.1 or 14.2 and the compatible ISE for that is ISE 7.1i for other compatible softwares search...
  3. r_a_c_a_4_u

    Recommend me a high level synthesis tools for FPGA

    looking for advice! you can use system generator ...it will giv you xilinx blocksets which can be converted to VHDL code and then you can implement it using system generator you will be able to simulate ... blocks from m file , coregen , vhdl files , verilog files ... all schematically ...
  4. r_a_c_a_4_u

    E-training for VLSI in India

    gud evng yea go ahead .... post in the write sub forum
  5. r_a_c_a_4_u

    Help me edit m file code for the black box

    i have implemented blocks in simulink using xilinx blocksets my all blocks are working with sample period of 769e-9 now i want my black box to work with this sample period what should i do i think i need to edit this code of the black box help ...needed ... thanx in advance!!! :D:D
  6. r_a_c_a_4_u

    I want phase shift in DDS output depending upon the input

    thnx very much echo ... i have system generator 7.1 and the model version of DDS is 1.4 im making a M-aryPSK transceiver with transmitter havin ROM ... so my input to DDS will be from ROM how to calculate this value of 32768 for pi radians ? Added after 1 hours 14 minutes: ok ok i got...
  7. r_a_c_a_4_u

    SDR and MATLAB Simulink

    sdr model in simulink what kind of code that model has with it ... i doubt if there will be a code with the model ... the model should run without it ...unless it has used black box (if xilinx blocksets are used)
  8. r_a_c_a_4_u

    I want phase shift in DDS output depending upon the input

    I m using a DDS (Xilinx block) and i am gettin a sine wave with sample period of 0.001 i have made the phase increment option in block parameter as register and im getting two new ports 'data' and 'we' ... so now i need to know how should i get a phase increment of pi radians ...what should...
  9. r_a_c_a_4_u

    Xilinx System Generator Help!!

    how to initialize data to block rom xilinx yea kavitha ... i had tried that but it din work for some unknown reason ... then i had to write a vhdl code and use a black box to get the data corresponding to a given address
  10. r_a_c_a_4_u

    not able to generate sine wave using DDS in simulink

    direct digital synthesis simulink help please .....
  11. r_a_c_a_4_u

    not able to generate sine wave using DDS in simulink

    dds sine table the diagram below shows my design to generate a sine wave ... but its not generating it .... help needed is there any need to create a lookup table inside the DDS block .. or its there by defalult ...? If it is required to create a lookup table manually then how it can...
  12. r_a_c_a_4_u

    Xilinx System Generator Help!!

    system generator sdr the problem im facing is the same ... i find no option in simulink/sysgen that will allow me to initialise my ROM with addresses and data corresponding each address .... if its not possible to initialise then how one would simulate the design using ROM ... and this code...

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