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Recent content by qy79

  1. Q

    Help : hierarchy LVS incorrect in PEX

    When doing hierarchical PEX , the LVS is incorrect with H-cells which is generated by H-cells analysis. In nmLVS , it is correct with H-cells. PEX warning --- there are most cells in hcell not found in layout - ignored and most cells listed in the xcell file has no device and will not be...
  2. Q

    inductor model in HSPICE

    ask it from foundry , it is important in rf design
  3. Q

    facing what challenge analog ic design in the future

    integrating RF ,mixsignal, and digital into one die
  4. Q

    the best ic design layout tools ?

    most use Cadence Virtuoso
  5. Q

    What is RFCMOS Technology ?

    it can provide inductor
  6. Q

    What circuits do you most often design ?

    What are you working on? high speed link
  7. Q

    How to ensure the duty equals 50% in PLL design?

    PLL duty cycle corrector inside PLL loop or outside ?
  8. Q

    How to implement DELAY in a circuit?

    more invertors more clock jitter due to supply noise
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