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Thank you for your reply.
But my question is comparison between 1000 and 1001 number of finger in schematic viewpoint. I mean the main ppint is odd and even number of finger.
I can not tell you what is the best book, but let me tell you something which I think it's the best for you in this case.
If I was you,
I will firstly clarify which problem do I have. What kind of design, knowledge do I want to know.
Then I will break down it and make some check list of things...
My mistake, even number of finger. Does it make more convinent for you to discuss?
Thank you for your replying. As I said, I know what is benefit from layout view point. Could you give some opinion form schematic view point?
Recently I have question about why we should choose even number of finger.
As far as I know, the even finger is easier to layout in Current Mirror, Differential Pair when we need matching. (Because we should abut, place common centroid etc,...)
But I want to know how about in schematic view...
Thank you. After trying some patterns of my layout, I think the horizontal one is a bit better, although the wiring is complex.
But as you said, it depends on actual design. The vertical pattern is good as well.
The second is seems better for matching when it has better common centroid.
One more thing is the number finger of A and B in the second configuration should be even for abut.
In my opinion, the second placement is good enough. It's simple for wiring and still get matching for A, B transitor.
There will be trade off when we choose too complex placement. Like wiring complexibility, parasitic resitor and capacitor...
In order to increase length of MOSFET, the schematic designer can connect multiple MOSFET as serial.
I would like to ask about this configuration in layout. Should I place MOSFET in vertical or horizontal?
Thank you.
I would like to ask how to find the formula of calculating resistance in Pcell?
For example, whenever I change the length, the resistance is automatically updated. How can I find it?
Thank you.
Thank you for sharing.
I know. But it has some cons. For example when my big layout is mess up with connection, the highlight net will mark incorrect. When I just want the Metal and Via layer only. Or when I want the output net is merged to Polygon shape, not Path shape.
I tried some options...
Just curious, I have Calibre tool for check almost everything of physical verification. But I still need more extraction check from diva tool.
For the one who does not know.
We can extract a signal from layout with diva rule. For example I would like to check all METAL and VIA layer of VSS...
Because the purpose of guard ring is separating all rfmos to other devices in circuit.
As long as you separate all rfmos (before or after), the protection purpose is satisfied.
In my opinion, it is safe to not add all guard ring in rfmos in the begining.
Let's consider about the priority of your layout requirement. If it put area higher than precise of guard ring protection, you can choose other normal mos without guard ring, layout them first by block or group, then...
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