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Recent content by QuIcK-SiLvEr

  1. Q

    Implementation using DSP and FPGA in a CDMA project

    Re: CDMA @eng well if u are to use Spartan starter kit for implementation …u must make sure how many gates it has..It depends XC3S200 has 2 million gates and .this means u cant implement a virtebi decoder on it which takes 37.8% space of XC3S1000(10 Million gates).Similarly a single channel...
  2. Q

    file on ext2 from NTFS or Win32 FAT

    and on fedora core 2?
  3. Q

    Sysgen error: netlist is empty. cannot trim useless hardware

    sysgen error!!! HI i use sysgen for my matlab code conversion to vhdl... but i am recieving an error which says... Netlist is empty...cannot trim useless hardware. and in result i only get a netlist file any clue?
  4. Q

    matlab code for FPGAs via system generator

    THANX Ok well it is possible to write our own code in matlab e.g for a FIR filter and convert it into a simulink library module...I dont want to use pre made modules of simulink .Im writing this because we have our own parameters and design constraints for programming over FPGAs... ..Question...
  5. Q

    matlab code for FPGAs via system generator

    Hi i plan to programme my spartan 3 fpga board with some simulink blocks... Im using system generator for this purpose. but i had doubts whether a block in simulink (simulation)eviroment could actually run on fpga board without any problems.. if there are any problems what they could be...

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