Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by qqxiu

  1. Q

    How sdc affect the sdf

    Hi ! Thanks to your reply. I was wondering if it is OK to provide less constraints in generating SDF. For example, we need to eliminate the set_case_analysis constraint. I want to know that which constraint should not be reduce in generating SDF.
  2. Q

    How sdc affect the sdf

    Hi all, After APR, i used Primetime to generate the sdf file for postsim. It seems that we need to prepare the sdc file to generate the sdf file. In my design, i have different mode, so i have different sdc file. I wondering that what kind of the sdc that is needed to generate a reliable sdf ...
  3. Q

    post sim without sdf

    Hi all, I'm new in VLSI. Recently, I run the postsim without sdf, that cause some of my test pattern failed. When I simulate with sdf, everything will be fine. I wondering why this will happened. Could anyone point out some knowledge that I miss? Thanks a lot.

Part and Inventory Search

Back
Top