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Recent content by qian15

  1. Q

    [SOLVED] Please Help Bugs in verilog code State Machine In Active HDl ?

    Is this you want?
  2. Q

    can we make FPGA kit ourself

    If you want ,you can.
  3. Q

    verilog problem in code

    Sorry,I don't konw your question
  4. Q

    AD9773 need help- how can I use 1port input and 2port output

    AD9773 need help HI,everybody I need help with AD9773.IN my project,a/d is used ad9238.Its input has tow chanel,but out put I use one chanel.So I use AD9773 as D/A. how can I use one port input and tow port output?I use FPGA connect the AD9773,how can I write the regiester?Can you help me?THANKS!
  5. Q

    How to create AWF file for the Aldec Active-hdl 8.1?

    HI,WeiGaoZu,I think I can help you. at the begining I have the same trouble,but last week,I have konw. You can select Tools--Preference-Waveform Viewer/Editor. At the right hand,select Standard Waveform Viewer/Editor. OK,you can create AWF file.
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