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Hi
I am having issues with PVS or Assura LVS checking the finger numbers of mosfets in the layout vs. schematic.
The LVS tool seems to ignore this parameter mismatches. Is there anyway to enable this function?
Thanks,
Thanks for your answers!
Other than this, is there any simple way to do it? how about switching different size of caps in parallel with fb res to limit the bandwidth?
Hi,
I am designing an amplifier in inverting configuration with variable gain.
But when switching the gain of by changing the value of the feedback resistor, the CL 3dB bandwidth also will change since the GBW is fixed. So how could I fixed the CL bandwidth?? acceptable variation will be +/-...
Hello,
I am designing a LPF which needs to achieve 50MHz with 20% accuracy(range 40MHz to 60MHz). The poly res and MIM cap all have ~20% variation over PVT, it is really hard to design such a LPF with simple RC. Can anybody suggests a circuit topology that can realize this LPF? Thank you very much!
Hello,
I would like to make virtual connection between two same nets while the name are different. I can find joint nets function in Assura but not in PVS, is anybody know how to do this in PVS?
Thank you
Hi guys,
I am gonna have a interview of post silicon validation job, they require DSP knowledge and control system, I dont really understand how they are going to ask me question about this two part, can anybody in this field give me some tips what kind of question will be asked for this job?
Open Cadence ADE
First, Chose the model Library you want to include
Eable DC analysis, AC analysis, noise analysis(Select the frequency you interest)
Then plot the AC magnitude and phase, you can check your GAIN, AC response, Phase margin here.
You can also plot the curve of noise
Plot the DC...
Why moving one of the nondominant pole towards orgin does not improve the phase margin?? Its the question in razavi's book(design of analog CMOS integrated circuit), I cant figure it out, can anybody explain it in detail? Its in the book P358.
Thanks in advance
Hi,
I am now working on designing APS, the column amplifer I am going to use is shown in the figure,
It seems like a switched capacitor amplifer, but why it do not have a switch between VSF and Cin, how it works to sample the input? The DC bias from output was blocked by the feedback capacitor...
As shown in the figure below, it has a capacitor feedback loop so that the dc voltage from input and output will be blocked at same time, so how can I supply dc bias to the input node of opamp?
Thanks!
Hi, I am designing a very simple two stage differential amplifier that posted on razavi's book, but the load is a 8 ohm resistor parallel with a 500fF cap, but when i connect it with the output, the AC response result become totally different!! It seems current flows in second stage flows into...
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