Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by pugongying

  1. P

    How does a Gilbert cell drive polyphase filter?

    passive RC polyphase filter low-IF, IF=4MHz,signal BW=2MHz Thx
  2. P

    How does a Gilbert cell drive polyphase filter?

    output impedance polyphase filter The Gilbert mixer has resistor load.(400ohm) Does the polyphase filter affect the linearity of the mixer? does the polyphase filter requires a low output impedance buffer?
  3. P

    How to evaluate the effect of higher order harmonic of LO signal in mixer simulation?

    When we simulate mixer,usually the LO signal is sine wave, but actually the LO signal may be square wave,so how to evaluate the effect of higher order harmonic of LO signal?
  4. P

    output capacitor of LDO

    output noise ldo What is the main contribution of LDO's large external output capacitor? Better transient response or low output noise? Or other reason? What about some on-chip LDO with small (<100pF) onchip output capacitor,do they have sever problems?
  5. P

    How to improve PSR of the bandgap?

    PSR of bandgap What is the reasonable power supply rejection of this bandgap structure? how can I improve PSR of the bandgap ?Thanks
  6. P

    current gain decrease in both high and low current?

    The current gain β=Ic/Ib is almost constant for moderate bias current,but if bias current is too high or too low,the β decreases,can anyone explain it ?expecially in terms of semiconductor device,thanks.
  7. P

    What kind of resistor do we use for LDO?

    In LDO,we require large resistors about 100k~200K ohm,can we use n-well resistor? How about the matching ?Thanks!
  8. P

    question on low drop out regulator

    voltage drop using NMOS is determined by VGS while using PMOS it is determined by VDS you can find the difference
  9. P

    How to improve LDO's transient response?

    transient responese of ldo Thanks to all of you,some suggestions really inspired me,and I finally confirmed that the main reason for large overshoot and undershoot is due to small capacitor, not phase margin or some other things. So,if I want to design an LDO for RF applications,off-chip large...
  10. P

    What HSPICE command will simulate LDO noise ?

    Re: LDO noise What is the source if we do .ac analysis? Do you mean the source is the input of the LDO?
  11. P

    How about these parameters as temperature increase?

    why threshold decrease as temperature rise? and I have found that above room temperature,electron mobility decrease as temperature increase because the scattering effect increases
  12. P

    How about these parameters as temperature increase?

    flicker noise MOS threshold voltage? PMOS/NMOS electron mobility
  13. P

    how does one capacitor charge another capacitor?

    Thanks! I agree with the initial value and final value,but how about the waveform? Is it linear some exponential or something?
  14. P

    Dc mismatch analysis????

    you should use monte carlo analysis if you have mismatch model in your PDK
  15. P

    how does one capacitor charge another capacitor?

    C1 has been connected to a voltage source V1 for a long time,at time 0,the switches switch the connection from V1 to C2,i.e. V1 is cutoff,and the two capacitor are parallel connected,what is the voltage waveform on C2? (all the capacitors and voltage source has one node connected to groud)

Part and Inventory Search